An oxide semiconductor thin film transistor using an oxide semiconductor which is typified by an indium-gallium-zinc oxide (hereinafter, referred to as InGaZnO) can achieve good electrical characteristics in a large area, as compared to a silicon-based semiconductor thin film transistor. In the following description, in some cases, a thin film transistor is abbreviated to TFT.
An oxide semiconductor TFT has started to be applied to a liquid crystal display and an organic electro-luminescence (EL) display. In the following description, the liquid crystal display is abbreviated to LCD. In addition, the organic EL display is abbreviated to OLED.
In recent years, a bottom-gate TFT has been mainly used as the oxide semiconductor TFT. A self-aligned top-gate TFT is advantageous when a large LCD or OLED is driven at a high speed. In the self-aligned top-gate TFT, low parasitic capacitance is generated in a region in which a gate electrode and a source electrode or a drain electrode overlap each other and a region in which the gate electrode and a source region or a drain region overlap each other.
FIG. 27 is a cross-sectional view schematically illustrating a self-aligned top-gate TFT disclosed in Japanese Patent Application Laid-Open No. 2007-220817. The self-aligned top-gate TFT includes a substrate 1, an oxide semiconductor layer 2, a gate insulating film 3, a gate electrode 4, a source-side contact hole 62, a drain-side contact hole 63, a source electrode 72, a drain electrode 73, and an interlayer insulating film 5. The oxide semiconductor layer 2 includes a channel region 21, a source region 22, and a drain region 23.
Japanese Patent Application Laid-Open No. 2007-220817 uses the properties of the oxide semiconductor in which hydrogen functions as a donor and resistance is variable. That is, a silicon nitride film containing a small amount of hydrogen is used as the gate insulating film 3 to reduce the amount of hydrogen in the channel region 21. Therefore, the high resistance of the channel region 21 is maintained. A silicon nitride film containing a large amount of hydrogen is used as the interlayer insulating film 5 to diffuse a large amount of hydrogen to the source region 22 and the drain region 23. Therefore, the resistance of the source region 22 and the drain region 23 is reduced.
Japanese Patent Application Laid-Open No. 2012-033836 discloses a top-gate TFT in which a gate electrode 4 has a function of suppressing the diffusion of hydrogen and the diffusion of hydrogen to a channel region 21 is suppressed when an interlayer insulating film 5 is formed.
In Japanese Patent Application Laid-Open No. 2007-220817 and Japanese Patent Application Laid-Open No. 2012-033836, the gate electrode 4 and the gate insulating film 3 are formed in the same pattern and hydrogen is diffused from the interlayer insulating film 5, using the pattern as a mask, to form the source region 22 and the drain region 23. Therefore, when the interlayer insulating film 5 is formed, the boundary between the channel region 21 and the source region 22 or the boundary between the channel region 21 and the drain region 23 is disposed immediately below the end of the gate electrode 4.
In order to reduce parasitic capacitance, it is necessary to suppress the diffusion of hydrogen from the source region 22 and the drain region 23 to the channel region 21 as much as possible.
H. Kitakado et al., “Channel Shortening Phenomenon Due to Redox Reaction in a Lateral Direction on In—Ga—Zn—O Thin-Film Transistors” (Proceedings of the eighteenth international workshop on Active-Matrix flat panel displays and devices—TFT technologies and FPD materials), 2011, p. 29 discloses a method for calculating a diffusion coefficient of hydrogen and the activation energy of hydrogen.
The diffusion coefficient of hydrogen and the activation energy can be calculated by Expressions (1) and Expression (2), respectively, on the basis of a model in which hydrogen is diffused from the source electrode 72 and the drain electrode 73 to an InGaZnO layer, which is an oxide semiconductor, to extend the source region 22 and the drain region 23.[Math. 1]Diffusion coefficient D(@350° C.)=1.2×10−12 cm−2s−1  (1)Activation energy Ea=0.66 eV  (2)
As described above, it is preferable to suppress the diffusion of hydrogen in the horizontal direction as much as possible in order to reduce parasitic capacitance. Therefore, the formation of the interlayer insulating film 5 and the subsequent annealing process are performed at a low temperature. As a result, it is difficult to ensure the reliability of the TFT. The reason is that, in general, the electrical characteristics and quality of the insulating film, which has been formed at a low temperature and has been subjected to annealing at a low temperature, are likely to deteriorate due to restrictions.
When the insulating film, of which the electrical characteristics have deteriorated, is used as the interlayer insulating film 5, hot carriers are likely to be injected into the drain end of the gate electrode 4. In addition, the quality of the insulating film deteriorates and the insulating film which is not dense is likely to contain water. The insulating film containing water is likely to be polarized and has low alkali metal contamination resistance. As a result, the characteristics of the TFT are likely to be shifted and an S value is likely to be reduced. Here, the S value is a gate voltage value in a sub-threshold region in which a drain current is changed by one digit when a drain voltage is constant.
When the formation of the interlayer insulating film 5 and annealing are performed at a high temperature in order to improve the reliability of the TFT, an excessive amount of hydrogen is diffused from the source region 22 and the drain region 23 to the channel region 21 in the horizontal direction. As a result, the area of the overlap between the gate electrode 4 and the source region 22, or of the overlap between the gate electrode 4 and the drain region 23 increases, which results in an increase in parasitic capacitance.
In a serious situation, hydrogen in the channel region 21 is diffused from the interlayer insulating film 5 over the gate electrode 4 and the gate insulating film 3 through the gate electrode 4 and the gate insulating film 3. Then, the number of carriers in the channel region 21 increases and a resistance value is reduced. As a result, the difference between the resistance values of the channel region 21 and the source region 22, or of the channel region 21 and the drain region 23 is reduced and the performance of the TFT is insufficient.